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2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs AD7912/AD7922
FEATURES
Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power: 4.8 mW typ at 1 MSPS with 3 V supplies 15.5mW typ at 1 MSPS with 5 V supplies Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI(R)/QSPITM/MICROWIRETM/DSP compatible Standby mode: 1 A maximum Daisy-chain mode 8-lead TSOT package 8-lead MSOP package
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN0 MUX VIN1 T/H
10-/12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK CS
AD7912/AD7922
CONTROL LOGIC
DOUT
04351-0-001
DIN
GND
APPLICATIONS
Battery-powered systems: Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors
Figure 1.
Several AD7912/AD7922 can be connected together in a daisy chain. The AD7912/AD7922 feature a daisy-chain mode that allows the user to read the conversion results from the ADCs contained in the chain. The AD7912/AD7922 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD, thereby allowing the widest dynamic input range to the ADC.
GENERAL DESCRIPTION
The AD7912/AD7922 are 10-bit and 12-bit, high speed, low power, 2-channel successive approximation ADCs, respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates of up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 6 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The conversion rate is determined by the SCLK signal. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. The channel to be converted is selected through the DIN pin, and the mode of operation is controlled by CS. The serial data stream from the DOUT pin has a channel identifier bit and mode identifier bit, which provide information about the converted channel and the current mode of operation.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
1
PRODUCT HIGHLIGHTS
1. 2-channel, 1 MSPS, 10-/12-bit ADCs in TSOT package. 2. High throughput with low power consumption. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Average power consumption is reduced when the power-down mode is used while not converting. Current consumption is 1 A maximum and 50 nA typically when in power-down mode. 4. Daisy-chain mode. 5. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
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Protected by U.S. Patent Number 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7912/AD7922 TABLE OF CONTENTS
Specifications..................................................................................... 3 AD7912 Specifications................................................................. 3 AD7922 Specifications................................................................. 5 Timing Specifications .................................................................. 7 Timing Diagrams.......................................................................... 7 Timing Examples.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Terminology .................................................................................... 11 Typical Performance Characteristics ........................................... 13 Circuit Information ........................................................................ 15 Converter Operation.................................................................. 15 ADC Transfer Function............................................................. 15 Typical Connection Diagram ................................................... 16 Analog Input ............................................................................... 16 Digital Inputs .............................................................................. 17 DIN Input.................................................................................... 17 DOUT Output ............................................................................ 17 Modes of Operation ....................................................................... 18 Normal Mode.............................................................................. 18 Power-Down Mode.................................................................... 18 Power-Up Time .......................................................................... 20 Daisy-Chain Mode ..................................................................... 20 Daisy-Chain Example ................................................................ 22 Power vs. Throughput Rate ........................................................... 24 Serial Interface ................................................................................ 25 Microprocessor Interfacing....................................................... 26 Application Hints ........................................................................... 28 Grounding and Layout .............................................................. 28 Evaluating AD7912/AD7922 Performance................................. 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7912/AD7922 SPECIFICATIONS
AD7912 SPECIFICATIONS
Temperature range for A Grade from -40C to +85C. VDD = 2.35 V to 5.25 V, fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Signal-to- Noise + Distortion (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error2 Offset Error Match2, 3 Gain Error2 Gain Error Match2, 3 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL A Grade1 61 -71 -72 -82 -83 10 30 90 8.5 1.5 10 0.5 0.5 0.5 0.3 0.5 0.3 0.5 0 to VDD 0.3 20 0.7 (VDD) 2 0.3 0.2 (VDD) 0.8 0.3 0.3 0.3 5 VDD - 0.2 0.2 0.3 5 Unit dB min dB max dB max dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max V A max pF typ V min V min V max V max V max A max A max A max pF max V min V max A max pF max Straight (natural) binary 2.35 V VDD 2.7 V 2.7 V < VDD 5.25 V VDD = 2.35 V 2.35 V < VDD 2.7 V 2.7 V < VDD 5.25 V Typically 8 nA, VIN = 0 V or VDD fa = 100.73 kHz, fb = 90.7 kHz fa = 100.73 kHz, fb = 90.7 kHz Test Conditions/Comments fIN = 100 kHz sine wave
@ 3 dB @ 0.1 dB
Guaranteed no missed codes to 10 bits
Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Current, IIN, DIN Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding
ISOURCE = 200 A, VDD = 2.35 V to 5.25 V ISINK = 200 A
Rev. 0 | Page 3 of 32
AD7912/AD7922
Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down A Grade1 777 290 1 2.35/5.25 3 1.5 4 2 1 0.48 0.26 20 6 5 Unit ns max ns max MSPS max V min/max mA typ mA typ mA max mA max A max mA typ mA typ mW max mW max W max Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS SCLK on or off, typically 50 nA VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS VDD = 5 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5 V Test Conditions/Comments 14 SCLK cycles with SCLK at 18 MHz
1 2
Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.
Rev. 0 | Page 4 of 32
AD7912/AD7922
AD7922 SPECIFICATIONS
Temperature range for A Grade from -40C to +85C. VDD = 2.35 V to 5.25 V, fSCLK = 18 MHz, fSAMPLE = 1 MSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 -0.9/+1.5 -0.7/+1.2 1 0.1 0.5 0.02 2 0.5 1 0.2 1.5 0.5 0 to VDD 0.3 20 0.7 (VDD) 2 0.3 0.2 (VDD) 0.8 0.3 0.3 0.3 5 LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ V A max pF typ V min V min V max V max V max A max A max A max pF max 2.35 V VDD 2.7 V 2.7 V < VDD 5.25 V VDD = 2.35 V 2.35 V < VDD 2.7 V 2.7 V < VDD 5.25 V Typically 8 nA, VIN = 0 V or VDD A Grade1 70 72 71 72.5 -81 -84 -84 -86 10 30 90 8.5 1.5 12 1.5 0.7 Unit dB min dB typ dB min dB typ dB typ dB typ dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB typ fa = 100.73 kHz, fb = 90.72 kHz fa = 100.73 kHz, fb = 90.72 kHz Test Conditions/Comments fIN = 100 kHz sine wave
@ 3 dB @ 0.1dB
Offset Error2 Offset Error Match2, 3 Gain Error2 Gain Error Match2, 3 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL
VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V Guaranteed no missed codes to 12 bits VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V VDD = 2.35 V to 3.6V VDD = 4.75 V to 5.25V
Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Current, IIN, DIN Pin Input Capacitance, CIN3
Rev. 0 | Page 5 of 32
AD7912/AD7922
Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down A Grade1 VDD - 0.2 0.2 0.3 5 Unit Test Conditions/Comments ISOURCE = 200 A; VDD = 2.35 V to 5.25 V ISINK = 200 A
V min V max A max pF max Straight (natural) binary ns max ns max MSPS max V min/max mA typ mA typ mA max mA max A max mA typ mA typ mW max mW max W max W max
888 290 1 2.35/5.25 3 1.5 4 2 1 0.5 0.28 20 6 5 3
16 SCLK cycles with SCLK at 18 MHz See the Serial Interface section
Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 1 MSPS SCLK on or off, typically 50 nA VDD = 5 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS VDD = 3 V, fSCLK = 18 MHz, fSAMPLE = 100 kSPS VDD = 5 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5 V VDD = 3 V
1 2 3
Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. See the Terminology section. Guaranteed by characterization. 4 See the Power vs. Throughput Rate section.
Rev. 0 | Page 6 of 32
AD7912/AD7922
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted. Table 3.
Parameter fSCLK1 tCONVERT tQUIET t1 t2 t33 t43 t5 t6 t74 t8 t9 t105 tPOWER-UP6 Limit at TMIN, TMAX 10 18 16 x tSCLK 14 x tSCLK 30 15 10 30 45 0.4 tSCLK 0.4 tSCLK 10 5 6 30 10 1 Unit kHz min2 MHz max AD7922 AD7912 Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until DOUT three-state is disabled DOUT access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to DOUT valid hold time DIN setup time prior to SCLK falling edge DIN hold time after SCLK falling edge SCLK falling edge to DOUT three-state SCLK falling edge to DOUT three-state Power-up time from full power-down Description
ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns max ns min s max
1 2 3
Mark/space ratio for SCLK input is 40/60 to 60/40. Minimum fSCLK at which specifications are guaranteed. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. 5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See the Power-Up Time section.
TIMING DIAGRAMS
200A IOL
SCLK
t7
TO OUTPUT PIN
1.6V
DOUT VIL
04351-0-004
CL 50pF 200A IOH
04351-0-002
VIH
Figure 2. Load Circuit for Digital Output Timing Specifications
Figure 4. Hold Time after SCLK Falling Edge
t4
SCLK
SCLK
t10
04351-0-003
DOUT VIL
DOUT
1.6V
Figure 3. Access Time after SCLK Falling Edge
Rev. 0 | Page 7 of 32
Figure 5. SCLK Falling Edge to DOUT Three-State
04351-0-005
VIH
AD7912/AD7922
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section.
Timing Example 2
The AD7922 can also operate with slower clock frequencies. As shown in Figure 7, when fSCLK = 5 MHz and the throughput rate is 315 kSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 3.17 s With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the requirement of 290 ns for tACQ. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET, satisfying the minimum requirement of 30 ns. In this example, as with other slower clock values, the signal might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7.
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput is 1 MSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 1 s With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the requirement of 290 ns for tACQ. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET, satisfying the minimum requirement of 30 ns.
t1
CS
t2
SCLK 1 2 3 4
tCONVERT t6
5 13
B
14 15 16
t3
DOUT DIN Z X ZERO X CHN MOD THREE-STATE
t4
DB11
t7
DB10 X DB2 X
t5
DB1 X DB0
t10
tQUIET
04351-0-006
04351-0-007
t8
CHN
t9
STY X X
THREE-STATE
Figure 6. AD7922 Serial Interface Timing Diagram
CS
t2
SCLK 1 2 3 4
tCONVERT
5 13
B
14
C
15 16
t10
12.5(1/fSCLK) 1/THROUGHPUT
tQUIET tACQUISITION
Figure 7. Serial Interface Timing Example
Rev. 0 | Page 8 of 32
AD7912/AD7922 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin except Supplies1 Operating Temperature Range Commercial (A Grade) Storage Temperature Range Junction Temperature TSOT Package JA Thermal Impedance MSOP Package JA Thermal Impedance JC Thermal Impedance Lead Temperature Soldering Reflow (10 s to 30 s) ESD Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 207C/W 205.9C/W 43.74C/W 235 (0/+5)C 1.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 9 of 32
AD7912/AD7922 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8-LEAD MSOP
DOUT CS SCLK DIN
1 2 3
8-LEAD TSOT
8 7
04351-0-008
6 VIN0 TOP VIEW 4 (Not to Scale) 5 VIN1
CS DOUT
6 GND TOP VIEW 4 (Not to Scale) 5 VDD 3
Figure 8. 8-Lead MSOP Pin Configuration
Figure 9. 8-Lead TSOT Pin Configuration
Table 5. Pin Function Descriptions
MSOP Pin No. 1 TSOT Pin No. 4 Mnemonic DOUT Function Data Out. Logic output. The conversion result from the AD7912/AD7922 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK signal. For the AD7922, the data stream consists of two leading zeros, the channel identifier bit that identifies which channel the conversion result corresponds to, followed by the mode bit that indicates the current mode of operation, followed by the 12 bits of conversion data with MSB first. For the AD7912, the data stream consists of two leading zeros, the channel identifier bit that identifies which channel the conversion result corresponds to, followed by the mode bit that indicates the current mode of operation, followed by the 10 bits of conversion data with MSB first and two trailing zeros. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7912/AD7922 and framing the serial data transfer. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7912/AD7922's conversion process. Data In. Logic input. The channel to be converted is provided on this input and is clocked into an internal register on the falling edge of SCLK. Analog Inputs. These two single-ended analog input channels are multiplexed into the on-chip track-and-hold amplifier. The analog input channel to be converted is selected by writing to the third MSB on the DIN pin. The input range is 0 to VDD. Analog Ground. Ground reference point for all circuitry on the AD7912/AD7922. All analog input signals should be referred to this GND voltage. Power Supply Input. The VDD range for the AD7912/AD7922 is from 2.35 V to 5.25 V.
2 3 4 6, 5
3 2 1 7, 8
CS SCLK DIN VIN0, VIN1
7 8
6 5
GND VDD
Rev. 0 | Page 10 of 32
04351-0-009
AD7912/ AD7922
VDD GND
DIN SCLK
1 2
AD7912/ AD7922
8 7
VIN1 VIN0
AD7912/AD7922 TERMINOLOGY
Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7912/ AD7922, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00...000) to (00... 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match The difference in offset error between any two channels. Gain Error The deviation of the last code transition (111...110) to (111...111) from the ideal, that is, VDD - 1 LSB after the offset error has been adjusted out. Gain Error Match The difference in gain error between any two channels. Total Unadjusted Error A comprehensive specification that includes gain error, linearity error, and offset error. Channel-to-Channel Isolation A measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal of 20 kHz to 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a 10 kHz signal. The figure is given worst case across both channels for the AD7912/AD7922. Track-and-Hold Acquisition Time The time required for the output of the track-and-hold amplifier to reach its final value within 1 LSB after the end of conversion. The track-and-hold amplifier returns to track mode at the end of conversion. See the Serial Interface section for more details. Signal-to-Noise + Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by 2, and the rms value for the quantization noise is q/12. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as
SNR = 6.02 N + 1.76 dB Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit converter, SNR is 62 dB. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental, which is defined as THD (dB) = 20 log where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
V 2 2 + V3 2 + V 4 2 + V 5 2 + V6 2 V1
The ratio of the rms value of the next largest component in the ADC output spectrum (up to fs /2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.
Rev. 0 | Page 11 of 32
AD7912/AD7922
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb).
The AD7912/AD7922 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and thirdorder terms are specified separately. The calculation of the intermodulation distortion is as in the THD specification, where it is defined as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.
Rev. 0 | Page 12 of 32
AD7912/AD7922 TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10 and Figure 11 show typical FFT plots for the AD7922 and AD7912, respectively, at a 1 MSPS sample rate and 100 kHz input frequency. Figure 12 shows the SINAD performance versus the input frequency for various supply voltages while sampling at 1 MSPS with a SCLK frequency of 18 MHz for the AD7922. Figure 13 shows the SNR performance versus the input frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 18 MHz for the AD7922. Figure 14 and Figure 15 show INL and DNL performance for the AD7922. Figure 16 shows a graph of the THD versus the analog input frequency for different source impedances when using a supply voltage of 3.6 V and a sampling rate of 1 MSPS. See the Analog Input section. Figure 17 shows a graph of the THD versus the analog input frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 18 MHz. Figure 18 shows the shutdown current versus the voltage supply for different operating temperatures.
5 8192 POINT FFT VDD = 2.7V FSAMP = 1MSPS FIN = 100kHz SNR = 73.1dB SINAD = 72.55dB THD = -81.78dB SFDR = -83.03dB
-67 VDD = 2.35V -68 VDD = 4.75V -69 VDD = 5.25V
-15
-35
SNR (dB)
SINAD (dB)
-70
-55
-71 VDD = 2.7V
-75
-72
04351-0-040
VDD = 3.6V -74 10 100 FREQUENCY (kHz)
-115
0
50
100
150
200 250 300 350 FREQUENCY (kHz)
400
450
500
1000
Figure 10. AD7922 Dynamic Performance at 1 MSPS
Figure 12. AD7922 SINAD vs. Input Frequency at 1 MSPS
-10
-30
8192 POINT FFT VDD = 2.7V FSAMP = 1MSPS FIN = 100kHz SNR = 61.88dB SINAD = 61.83dB THD = -81.12dB SFDR = -84.92dB
-71.6 VDD = 2.35V -71.8 -72.0 VDD = 5.25V -72.2 -72.4 -72.6 -72.8 -73.0 VDD = 4.75V VDD = 3.6V
SNR (dB)
-50
-70
-90
04351-0-041
SNR (dB)
-73.2 -73.4 -73.6 10 VDD = 2.7V 100 FREQUENCY (kHz)
04351-0-044
-110
0
50
100
150
200 250 300 350 FREQUENCY (kHz)
400
450
500
1000
Figure 11. AD7912 Dynamic Performance at 1 MSPS
Figure 13. AD7922 SNR vs. Input Frequency at 1 MSPS
Rev. 0 | Page 13 of 32
04351-0-043
-95
-73
AD7912/AD7922
1.0 0.8 0.6 0.4 VDD = 2.7V FSAMP = 1MSPS TEMPERATURE = 25C -68 -70 -72 VDD = 2.35V -74 VDD = 2.7V VDD = 4.75V
INL ERROR (LSB)
THD (dB)
0.2 0 -0.2 -0.4 -0.6
04351-0-045
-76 -78 -80 VDD = 3.6V -82 -84 -86 -88 10 100 FREQUENCY (kHz)
04351-0-048
VDD = 5.25V
-0.8 -1.0 0 512 1024 1536 2048 CODE 2560 3072 3584
4096
1000
Figure 14. AD7922 INL Performance
Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages
1.0 0.8 0.6 VDD = 2.7V FSAMP = 1MSPS TEMPERATURE = 25C
180 160
SHUTDOWN CURRENT (nA)
140 TEMP = +85C 120 100 80 60 40 TEMP = +25C 20 TEMP = -40C 0 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0
04351-0-049
DNL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 CODE 2560 3072 3584
04351-0-046
4096
5.5
Figure 15. AD7922 DNL Performance
-20 VDD = 3.6V -30 -40
Figure 18. Shutdown Current vs. Supply Voltage
RIN = 1k
THD (dB)
-50
-60 RIN = 500 -70
RIN = 100 RIN = 50 RIN = 10
04351-0-047
-80 RIN = 0 -90 10 100 FREQUENCY (kHz)
1000
Figure 16. THD vs. Analog Input Frequency for Various Source Impedances
Rev. 0 | Page 14 of 32
AD7912/AD7922 CIRCUIT INFORMATION
The AD7912/AD7922 are fast, 2-channel, 10-/12-bit, single supply, analog-to-digital converters (ADCs), respectively. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7912/AD7922 are capable of throughput rates of 1 MSPS when provided with an 18 MHz clock. The AD7912/AD7922 provide the user with an on-chip trackand-hold, an ADC, and a serial interface, all housed in a tiny 8-lead TSOT package or 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the parts, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC. The analog input range is 0 to VDD. An external reference is not required for the ADC, and neither is there a reference on-chip. The reference for the AD7912/AD7922 is derived from the power supply and, therefore, gives the widest dynamic input range. The AD7912/AD7922 feature a power-down option that allows power saving between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. The AD7912/AD7922 can also be used in daisy-chain mode when several AD7912/AD7922 are connected in a daisy chain. This mode of operation is selected by controlling the logic state of the CS signal. The fourth MSB on the DOUT pin indicates if the ADC is in normal mode or daisy-chain mode. When the ADC starts a conversion (see Figure 20), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 21 shows the ADC transfer function.
CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR CONVERSION PHASE VDD/2 AGND SW2 COMPARATOR CONTROL LOGIC
04351-0-017
VIN0 VIN1
A SW1 B
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7912/AD7922 is straight binary. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSBs, and so on. The LSB size is VDD/4096 for the AD7922 and VDD/1024 for the AD7912. The ideal transfer characteristic for the AD7912/AD7922 is shown in Figure 21.
CONVERTER OPERATION
The AD7912/AD7922 are 10-/12-bit successive approximation ADCs based around a charge redistribution DAC. Figure 19 and Figure 20 show simplified schematics of the ADC. Figure 19 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on the selected VIN channel.
CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR ACQUISITION PHASE VDD/2 AGND SW2 COMPARATOR CONTROL LOGIC
04351-0-016
111...111 111...110
ADC CODE
111...000 011...111 1LSB = VREF/4096 (AD7922) 1LSB = VREF/1024 (AD7912)
04351-0-018
000...010 000...001 000...000 0V 1LSB ANALOG INPUT +VDD - 1LSB
Figure 21. AD7912/AD7922 Transfer Characteristic
VIN0 VIN1
A SW1 B
Figure 19. ADC Acquisition Phase
Rev. 0 | Page 15 of 32
AD7912/AD7922
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the AD7912/ AD7922. VREF is taken internally from VDD and as such VDD should be well decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with two leading zeros, followed by the channel identifier bit that identifies the channel converted, followed by the mode bit that indicates the current mode of operation, and by the MSB of the 12-bit or 10-bit result. For the AD7912, the 10-bit result is followed by two trailing zeros. See the Serial Interface section. Alternatively, because the supply current required by the AD7912/AD7922 is so low, a precision reference can be used as the supply source to the AD7912/AD7922. A REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This configuration is especially useful, if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V (for example, 15 V). The REF19x outputs a steady voltage to the AD7912/AD7922. If the low dropout REF193 is used, the current it needs to supply to the AD7912/ AD7922 is typically1.5 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 needs to supply a maximum of 2 mA to the AD7912/AD7922. The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which results in an error of 20 ppm (60 V) for the 2 mA drawn from it. This corresponds to a 0.082 LSB error for the AD7922 with VDD = 3 V from the REF193 and a 0.061 LSB error for the AD7912. For applications where power consumption is a concern, the power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See the Modes of Operation section.
3V 1.5mA 680nF VDD 0V TO VDD INPUT VIN0 VIN1 GND 0.1F 1F TANT REF193 10F 0.1F 5V SUPPLY
Table 6 provides some typical performance data with various references used as a VDD source and a 50 kHz input tone under the same setup conditions.
Table 6. AD7922 Performance for Various Voltage References IC
Reference Tied to VDD AD780 at 3 V REF193 ADR433 AD780 at 2.5 V REF192 ADR421 AD7922 SNR Performance (dB) -73 -72.42 -72.9 -72.86 -72.27 -72.75
ANALOG INPUT
Figure 23 shows an equivalent circuit of the analog input structure of the AD7912/AD7922. The two diodes, D1 and D2, provide ESD protection for the analog input. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV, because this would cause these diodes to become forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 10 mA.
VDD D1 VIN C1 6pF D2
04351-0-020
R1
C2 20pF
Figure 23. Equivalent Analog Input Circuit
AD7912/ AD7922
SCLK CS DIN DOUT
C/P
04351-0-019
The capacitor C1 in Figure 23 is typically about 6 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of the track-and-hold switch and also includes the on resistance of the input multiplexer. This resistor is typically about 100 . The capacitor C2 is the ADC sampling capacitor and has a capacitance of 20 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended using a band-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances can significantly affect the ac performance of the ADC. This might necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.
SERIAL INTERFACE
Figure 22. REF193 as Power Supply to AD7912/AD7922
Rev. 0 | Page 16 of 32
AD7912/AD7922
Table 7 provides some typical performance data with various op amps used as the input buffer, and a 50 kHz input tone under the same setup conditions.
Table 7. AD7922 Performance for Various Input Buffers
Op Amp in the Input Buffer Single op amps AD8038 AD8510 AD8021 Dual op amps AD712 AD8022 AD7922 SNR Performance (dB) 50 kHz Input , VDD = 3.6 V -72.79 -72.35 -72.2 -72.68 -72.88
The fourth MSB, STY, is related to the mode of operation of the device. To keep the AD7912/ AD7922 in daisy-chain mode, the CHN and STY bits have to be inverted during the conversions (STY CHN). A conversion with STY = CHN on the input forces the device to normal mode in the next cycle. See the Daisy-Chain Mode section for more details. If the AD7912/AD7922 are not going to be used in daisy-chain mode, it is recommended to keep STY and CHN the same (STY = CHN). In that case, the channel can be selected by tying DIN either high or low during a conversion cycle. To summarize:
CHN = 0, Channel 0 selected for next conversion. CHN = 1, Channel 1 selected for next conversion. CHN = STY, forces normal mode in the next cycle. CHN STY, keeps the AD7912/AD7922 in daisy-chain mode.
MSB X X CHN STY DON'T CARE LSB
04351-0-021
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades (see Figure 16).
DIGITAL INPUTS
The digital inputs applied to the AD7912/AD7922 are not limited by the maximum ratings that limit the analog input. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7912/AD7922 are operated with a VDD of 3 V, then 5 V logic levels could be used on the digital inputs. However, it is important to note that the data output on DOUT still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK, DIN, and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS, DIN, or SCLK are applied before VDD, then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to VDD.
Figure 24. AD7912/AD7922 DIN Word
DOUT OUTPUT
The conversion result from the AD7912/AD7922 is provided on this output as a serial data stream. The bits are clocked out on the SCLK falling edge at the same time that the conversion is taking place. The serial data stream for the AD7922 consists of two leading zeros followed by the bit that identifies the channel converted, the bit that indicates the current mode of operation, and the 12-bit conversion result with MSB provided first. For the AD7912, the serial data stream consists of two leading zeros followed by the bit that identifies the channel converted, the bit that indicates the current mode of operation, and the 10-bit conversion result with MSB provided first, followed by two trailing zeros. The CHN and MOD bits on DOUT indicate to the user the current mode of operation of the ADC. If CHN = MOD, the AD7912/AD7922 are in normal mode. Otherwise, if CHN MOD, the AD7912/AD7922 are in daisy-chain mode.
MSB LSB 0 CHN MOD CONVERSION RESULT 0 0 0
DIN INPUT
The channel to be converted on in the next conversion is selected by writing to the DIN pin. Data on the DIN pin is loaded into the AD7912/AD7922 on the falling edge of SCLK. The data is transferred into the part on the DIN pin at the same time that the conversion result is read from the part. Only the third and fourth bits of the DIN word are used; the rest are ignored by the ADC. The third MSB is the channel identifier bit, which identifies the channel to be converted on in the next conversion, VIN0 (CHN = 0) or VIN1 (CHN = 1).
AD7912 AD7922
04351-0-022
0
0
CHN MOD
CONVERSION RESULT
Figure 25. AD7912/AD7922 DOUT Word
Rev. 0 | Page 17 of 32
AD7912/AD7922 MODES OF OPERATION
The three modes of operation of the AD7912/AD7922 are normal mode, power-down mode, and daisy-chain mode. The mode of operation is selected by controlling the logic state of the CS signal. The point at which CS is pulled high after the conversion has been initiated determines whether the AD7912/AD7922 enter power-down mode or change to daisychain mode. Similarly, if already in daisy-chain mode, CS can control whether the device returns to normal operation or enters power-down mode. The user can also change from daisychain mode to normal mode by writing to the DIN pin, as outlined in the DIN Input section. Power-down mode is designed to provide flexible power management options and to optimize the ratio of power dissipation to throughput rate for different application requirements. Daisy-chain mode is intended for applications where fast throughput rate is not required and more than one AD7912/AD7922 have been connected in a daisy chain, as shown in Figure 33. CS can idle high until the next conversion or can idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (DOUT has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again.
POWER-DOWN MODE
Power-down mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions can be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7912/ AD7922 are in power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 28. Once CS has been brought high in this window of SCLKs, then the part enters power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and DOUT goes back into three-state. If CS is brought high before the second SCLK falling edge, then the part remains in normal mode and does not power down. This helps to avoid accidental power-down due to glitches on the CS line. To exit this mode of operation and power the AD7912/AD7922 up again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs have elapsed and valid data results from the next conversion, as shown in Figure 29. If CS is brought high before the 10th falling edge of SCLK, then the AD7912/AD7922 go back into powerdown mode. This helps to avoid accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. Therefore, although the device might begin to power up on the falling edge of CS, it powers down again on the rising edge of CS, as long as this occurs before the 10th SCLK falling edge.
NORMAL MODE
Normal mode is intended for the fastest throughput rate performance. The user does not have to worry about any power-up time, because the AD7912/AD7922 remain fully powered all the time. Figure 26 shows the operation of the AD7912/AD7922 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high after the 10th SCLK falling edge and before the 12th SCLK falling edge, then the device enters daisy-chain mode, as shown in Figure 27. The conversion is terminated and DOUT goes back into three-state. If CS is brought high after the 13th SCLK falling edge, but before the end of tCONVERT, the conversion is terminated and DOUT goes back into three-state, but the part remains in normal mode. For the AD7922, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7912, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result.
Rev. 0 | Page 18 of 32
AD7912/AD7922
AD7912/AD7922
CS 1 SCLK 10 12 14 16 1 10 12 14 16
DIN
CHANNEL FOR NEXT CONVERSION
CHANNEL FOR NEXT CONVERSION
04351-0-023
04351-0-024
DOUT
CONVERSION RESULT
CONVERSION RESULT
Figure 26. Normal Mode Operation
THE PART ENTERS DAISY-CHAIN MODE CS
1 SCLK
2
10
12
16
THREE-STATE DIN INVALID DATA THREE-STATE DOUT INVALID DATA
04351-0-025
Figure 27. Entering Daisy-Chain Mode
CS
1 SCLK
2
10
16
DIN
THREE-STATE INVALID DATA THREE-STATE
DOUT
INVALID DATA
Figure 28. Entering Power- Down Mode
THE PART BEGINS TO POWER UP THE PART GOES INTO TRACK CS
THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED NORMAL MODE
1 SCLK
A5
10
13
16
1
16
DIN
CHANNEL FOR NEXT CONVERSION
CHANNEL FOR NEXT CONVERSION
04351-0-026
DOUT
INVALID DATA
CONVERSION RESULT
Figure 29. Exiting Power-Down Mode
Rev. 0 | Page 19 of 32
AD7912/AD7922
POWER-UP TIME
The power-up time of the AD7912/AD7922 is 1 s, which means that with any frequency of SCLK up to 18 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is fully acquired. The quiet time, tQUIET, must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at a 1 MSPS throughput rate, the AD7912/AD7922 power up and acquire a signal within 1 LSB in one dummy cycle, that is, 1 s. When powering up from power-down mode with a dummy cycle, as in Figure 29, the track-and-hold that was in hold mode while the part was powered down returns to track mode on the fifth SCLK falling edge that the part receives after the falling edge of CS. This is shown as point A in Figure 29. At this point, the part starts to acquire the signal on the channel selected in the current dummy conversion. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully. 1 s is sufficient to power up the device and acquire the input signal. For example, if a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 s. In one dummy cycle, 3.2 s, the part would be powered up and VIN acquired fully. However, after 1 s with a 5 MHz SCLK, only five SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal is acquired. Therefore, in this case, CS can be brought high after the 10th SCLK falling edge. If CS is brought high anytime after the 13th SCLK falling edge, the part enters normal mode for the next conversion. CS has to be brought low again after a time, tQUIET, to initiate the conversion. However, if CS is brought high anytime after the 10th and before the 12th SCLK falling edge, the part enters daisy-chain mode. When power supplies are first applied to the AD7912/AD7922, the ADC can power up in either power-down mode, normal mode, or daisy-chain mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the user wants to keep the part in power-down mode while not in use and to power up in power-down mode, then the dummy cycle can be used to ensure that the device is in power-down mode by executing a cycle such as that shown in Figure 28. Once supplies are applied to the AD7912/AD7922, the powerup time is the same as when powering up from the power-down mode. It takes the part approximately 1 s to power up fully in normal mode. It is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. When the ADC powers up initially after supplies are applied, the track-and-hold is in hold. It returns to track on the fifth SCLK falling edge that the part receives after the falling edge of CS.
DAISY-CHAIN MODE
When the ADC is in this mode of operation, the part operates as a shift register. This mode is intended for applications where more than one ADC is used, connected in a daisy-chain configuration (see Figure 33). All ADCs are addressed by the same CS signal and the same serial clock. The conversion result stored in the internal shift register in each ADC is shifted from one device to the following in the chain. See the Daisy-Chain Example in the following section for more details. To enter daisy-chain mode, the conversion process must be interrupted by bringing CS high after the 10th falling edge of SCLK and before the 12th falling edge of SCLK, as shown in Figure 27. To ensure that the AD7912/AD7922 are placed into daisy-chain mode, CS should not be brought high until at least 20 ns after the 10th SCLK falling edge and before the 12th SCLK falling edge. Once CS has been brought high in this window of SCLKs, the part enters daisy-chain mode, the conversion that was initiated by the falling edge of CS is terminated, and DOUT goes back into three-state. If CS is brought high between the 10th and the 12th SCLK falling edge, the part enters daisy-chain mode and the data shifted from one ADC to the next one in the chain is valid data (see Figure 34 and Figure 35). If CS is brought high between the 12th and the 13th SCLK falling edge, the part enters daisy-chain mode, but the data shifted in the chain is invalid data. To keep the part in daisy-chain mode, the CHN and STY bits in the DIN word must be inverted relative to each other in each 16 SCLKs cycle. A conversion with the CHN and STY bits set to the same value in the DIN word while the device is in daisychain mode forces the part to go back into normal mode in the next cycle, as shown in Figure 30. To exit this mode of operation, the user can perform a dummy cycle or can set the STY bit to the CHN bit value on the DIN word during a conversion cycle. When performing a dummy conversion to exit this mode, CS must be brought high anytime after the 10th SCLK falling edge and before the 13th SCLK falling edge, as shown in Figure 31. The device enters normal mode, and valid data from the channel selected in the dummy cycle results in the next conversion. Figure 32 summarizes the modes of operation, how to change between modes, the values for the bits in the DIN and DOUT words in different modes, and in the transitions between modes.
Rev. 0 | Page 20 of 32
AD7912/AD7922
CS 1 SCLK DAISY-CHAIN CYCLE NORMAL MODE
10
12
14
16
1
10
12
14
16
DIN
CH = STY
CHANNEL FOR NEXT CONVERSION
04351-0-028
DOUT
VALID DATA
CONVERSION RESULT
Figure 30. Exiting Daisy-Chain Mode with CH = STY in the DIN Pin
THE PART ENTERS NORMAL MODE CS NORMAL MODE
A1
SCLK
10
13
16
1
16
DIN
CHANNEL FOR NEXT CONVERSION
CHANNEL FOR NEXT CONVERSION
04351-0-027 04351-0-029
DOUT
INVALID DATA
CONVERSION RESULT
Figure 31. Exiting Daisy-Chain Mode
CS HIGH BETWEEN THE 10TH-13TH SCLK CONVERSION CYCLE CONVERSION CYCLE CONVERSION CYCLE NORMAL MODE
DIN: CHN STY
DIN: CHN = STY
DOUT: CHN = MOD
*CS HIGH BETWEEN THE 10TH-12TH SCLK POWER-UP TIME AND CS HIGH AFTER THE 13TH SCLK
DOUT:CHN MOD
DAISY-CHAIN MODE
CS HIGH BETWEEN THE 2ND-10TH SCLK POWER-DOWN MODE
CS HIGH BETWEEN THE 2ND-10TH SCLK
POWER-UP TIME AND CS HIGH BETWEEN THE 10TH-12TH SCLK
*IF CS IS BROUGHT HIGH BETWEEN THE 10TH AND THE 12TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS VALID DATA. IF CS IS BROUGHT HIGH BETWEEN THE 12TH AND THE 13TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS INVALID DATA.
Figure 32. Transitions between Modes of Operation
Rev. 0 | Page 21 of 32
AD7912/AD7922
DAISY-CHAIN EXAMPLE
In applications where fast throughput is not critical, connecting several ADCs in a daisy chain lets the user perform simultaneous sampling on all the ADCs contained in the chain using the minimum number of I/O lines from the C/DSP ports. The user needs to alternate modes of operation in the ADCs. While the parts are in normal mode, the conversion is performed and the result from each ADC is stored in its internal register. Following the conversion, the parts are placed into daisy-chain mode and the user can proceed to read the result from each ADC by shifting the data from one ADC to the next. For clarity in the following example, only two devices are connected in a daisy chain. Both AD7912/AD7922 are addressed by the same CS and SCLK signal. The devices are configured as shown in Figure 33 for simultaneous conversion and shifting read operation later. The output of the device on the left, ADC1, feeds the input of the device on the right, ADC2. During a normal conversion, the conversion result is stored internally and output to the DOUT pin. In daisy-chain mode, the value internally stored is output through the DOUT pin and the information provided at the DIN pin is shifted into the internal register. When several AD7912/AD7922 are connected in a daisy chain, the sequence is as follows: 1.
Normal conversion. Every AD7912/AD7922 performs a conversion on its selected channel and the result is stored in the internal shift register. Entering daisy-chain mode. In this cycle, CS is brought high between the 10th and 12th SCLK falling edges and all the devices enter daisychain mode. Daisy-chain cycles. While the AD7912/AD7922 are in daisy-chain mode, the conversion results from all the devices in the chain are read, and the parts are configured for the next conversion.
tion data for the second last device in the chain, and so on. Then the selected channel for the first device in the chain is clocked in the cycle executed after all the data has been read, that is, in the short cycle used to change modes of operation. See Figure 34. 4.
Enter normal mode. After reading the conversion results from the AD7912/ AD7922, the devices need to be placed into normal mode to perform a new conversion. Therefore, in this cycle CS is brought high between the 10th and the 13th SCLK falling edge. The DOUT line contains invalid data and DIN contains the selected channel for the first device in the chain. The remaining devices in the chain have already set the channel for the next conversion as a result of the data shifted in during daisy-chain mode. Normal conversion. A new conversion can be performed on the newly selected channels. The process can be repeated by following the previous steps.
5.
2.
Figure 34 shows the timing diagram for two AD7912/ AD7922 connected in a daisy chain, as shown in Figure 33. The DIN signal corresponds to the DIN pin on the first AD7912/AD7922 in the chain, and the DOUT signal corresponds to the DOUT pin on the last AD7912/AD7922 in the chain. The words clocked into the DIN pin, which set up the channel for the next conversion for the two AD7912/AD7922, are shown as COMMAND1 and COMMAND2. The first word clocked in, COMMAND3, does not remain in any of the ADCs in the chain and is eventually lost. The channel configuration data for the first device in the chain, COMMAND1, is clocked in while changing from daisy-chain mode to normal mode. Figure 35 is a more detailed diagram that shows the data presented on the DIN pin and clocked out on the DOUT pin for each of the AD7912/AD7922 in Figure 33. If the DOUT1 (or DIN2) signal is ignored, Figure 35 brings about Figure 34.
FSX SCLK C/DSP TX DIN
SCLK CS
3.
The user needs to perform as many read cycles as there are devices in the chain. To keep all the AD7912/AD7922 in daisy-chain mode, the CHN and STY bits in the DIN input must always be inverted. Data is shifted through the devices in the chain. Data is clocked into the device in the chain by the same clock used to clock data out. The first word clocked into the DIN pin once the devices are in daisy-chain mode is eventually lost. The second word clocked into the DIN pin contains the channel configuration data for the last device in the chain, the third word clocked into the DIN pin contains the channel configura-
SCLK DIN1
CS DOUT1
SCLK DIN2
CS DOUT2
DOUT
04351-0-030
ADC1 DR
ADC2
Figure 33. AD7912/AD7922 Connected in Daisy Chain
Rev. 0 | Page 22 of 32
AD7912/AD7922
NORMAL MODE CONVERSION ON THE TWO DEVICES CS SCLK THE DATA WILL BE EVENTUALLY LOST, COMMAND3 DIN DON'T CARE DON'T CARE CH STY SET CHANNEL FOR ADC2, COMMAND2 CH STY SET CHANNEL FOR ADC1, COMMAND1 DON'T CARE DON'T CARE CHANGE MODE CS HIGH BETWEEN THE 10TH-12TH SCLK FALLING EDGE DAISY-CHAIN MODE DATA IS SHIFTED FROM ONE ADC TO THE NEXT ONE DAISY-CHAIN MODE DATA IS SHIFTED FROM ONE ADC TO THE NEXT ONE CHANGE MODE CS HIGH BETWEEN THE 10TH-13TH SCLK FALLING EDGE NORMAL MODE CONVERSION ON THE TWO DEVICES
DOUT
DON'T CARE
DON'T CARE
VALID DATA ADC2
VALID DATA ADC1
DON'T CARE
DON'T CARE
Figure 34. Daisy-Chain Diagrams--1
THE PARTS ENTER DAISY-CHAIN MODE CS 1 SCLK DON'T CARE DON'T CARE COMMAND3 WITH CHN STY SHIFTED INTO THE ADC1 INTERNAL REGISTER, THIS DATA WILL BE EVENTUALLY LOST DOUT1 (DIN2)* 0, 0, CHN = MOD, VALID DATA ADC1 (0, 0, CHN = STY, VALID DATA ADC1) DON'T CARE 0, 0, CHN MOD, VALID DATA ADC1 (0, 0, CHN STY, VALID DATA ADC1) SHIFTED INTO THE ADC2 INTERNAL REGISTER DOUT 0, 0, CHN = MOD, VALID DATA ADC2 DON'T CARE 0, 0, CHN MOD, VALID DATA ADC2 NORMAL CONVERSION 16 1 10 12 1 DAISY-CHAIN CYCLE 10 12 14 16
DIN
THE PARTS ENTER NORMAL MODE CS 1 SCLK DAISY-CHAIN CYCLE 10 12 14 16 1 10 13 1 NORMAL CONVERSION 16
DIN
COMMAND2 WITH CHN STY SHIFTED INTO THE ADC1 INTERNAL REGISTER
COMMAND1
DON'T CARE SHIFTED INTO THE ADC1 INTERNAL REGISTER, IT CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1 0, 0, CHN = MOD, VALID DATA ADC1 (0, 0, CHN = STY, VALID DATA ADC1) SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2
DOUT1 (DIN2)*
COMMAND3 SHIFTED INTO THE ADC2 INTERNAL REGISTER 0, 0, CHN MOD, VALID DATA ADC1
COMMAND2
DOUT
COMMAND3
0, 0, CHN = MOD, VALID DATA ADC2
04351-0-032
NOTE *INFORMATION IN BRACKETS CORRESPONDS TO DATA CLOCKED INTO DIN2 PIN
Figure 35. Daisy-Chain Diagrams--II
Rev. 0 | Page 23 of 32
04351-0-031
KEEP THE DEVICES IN DAISY-CHAIN MODE
AD7912/AD7922 POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7912/AD7922 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 36 shows how, as the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time drops. For example, if the AD7912/AD7922 are operating in a continuous sampling mode with a throughput rate of 100 kSPS and a SCLK of 18 MHz (VDD = 5 V), and the devices are placed in the power-down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 20 mW (VDD = 5 V). If the power-up time is one dummy cycle (1 s), and the remaining conversion time is another cycle (1 s), then the AD7912/AD7922 dissipate 20 mW for 2 s during each conversion cycle. If the throughput rate is 100 kSPS and the cycle time is 10 s, then the average power dissipated during each cycle is (2/10) x (20 mW) = 4 mW If VDD = 3 V, SCLK = 18 MHz, and the device is again in powerdown mode between conversions, then the power dissipation during normal operation is 6 mW. The AD7912/AD7922 now dissipate 6 mW for 2 s during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (2/10) x (6 mW) = 1.2 mW
POWER (mW) 1 VDD = 3V, SCLK = 18MHz
In the previous calculations, the power dissipation when the part is in power-down mode has not been taken into account. By placing the parts into power-down mode between conversions, the average power consumed by the ADC decreases as the throughput rate decreases, because the ADC remains in a power-down state for a longer time. Figure 36 shows the power consumption versus throughput rate when using the power-down mode between conversions with both 5 V and 3 V supplies. Power-down mode is intended for use with throughput rates of approximately 330 kSPS and under, because at higher sampling rates the short time spent in power-down does not affect the average power consumed by the ADC.
100
10
VDD = 5V, SCLK = 18MHz
0.1
04351-0-033
0.01
0
50
100
150 200 250 THROUGHPUT (kSPS)
300
350
Figure 36. Power Consumption vs. Throughput Rate
Rev. 0 | Page 24 of 32
AD7912/AD7922 SERIAL INTERFACE
Figure 37 and Figure 38 show the detailed timing diagrams for serial interfacing to the AD7922 and AD7912, respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7912/AD7922 during conversion. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state. The analog input is sampled at this point and the conversion is initiated. For the AD7922, the conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next SCLK rising edge, as shown in Figure 37 at Point B. On the 16th SCLK falling edge, the DOUT line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, then the conversion is terminated and the DOUT line goes back into three-state. Otherwise, DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 37. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7922. For the AD7912, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next SCLK rising edge, as shown in Figure 38 at Point B. If the rising edge of CS occurs before 14 SCLKs have elapsed, then the conversion is terminated and the DOUT line goes back into three-state. If 16 SCLKs are considered in the cycle, DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 38. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero. Therefore, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge. In that case, the first falling edge of SCLK clocks out the second leading zero and it can be read in the first rising edge. However, the first leading zero that is clocked out when CS goes low is missed, unless it is read on the first falling SCLK edge. The 15th falling edge of SCLK clocks out the last bit and it can be read in the 15th rising SCLK edge. If CS goes low just after the SCLK falling edge has elapsed, CS clocks out the first leading zero as before and it can be read in the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero and it can be read in the following rising edge.
t1
CS
t2
SCLK 1 2 3 4
tCONVERT t6
5 13
B
14 15 16
t3
DOUT DIN Z X ZERO X CHN MOD THREE-STATE
t4
DB11
t7
DB10 X DB2 X
t5
DB1 X DB0
t10
tQUIET
04351-0-034
t8
CHN
t9
STY X X
THREE-STATE
Figure 37. AD7922 Serial Interface Timing Diagram
t1
CS
t2
SCLK 1 2 3 4
tCONVERT t6
5 13
B
14 15 16
t3
DOUT DIN Z X ZERO X CHN MOD THREE-STATE
t4
DB9
t7
DB8 X X DB0 X
t5
ZERO X ZERO
t10
tQUIET
04351-0-035
t8
CHN
t9
STY
TWO TRAILING ZEROS X
THREE-STATE
Figure 38. AD7912 Serial Interface Timing Diagram
Rev. 0 | Page 25 of 32
AD7912/AD7922
MICROPROCESSOR INTERFACING
The serial interface on the AD7912/AD7922 allows the parts to be directly connected to a range of microprocessors. This section explains how to interface the AD7912/AD7922 with some of the more common microcontroller and DSP serial interface protocols.
AD7912/AD7922 to ADSP-218x
The ADSP-218x family of DSPs are interfaced directly to the AD7912/AD7922 without any glue logic required. The SPORT control register should be set up as follows: TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right-justify data ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0, set up RFS as an input ITFS = 1, set up TFS as an output SLEN = 1111, 16 bits for the AD7922 SLEN = 1101, 14 bits for the AD7912 To implement the power-down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 40. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described previously. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling might not be achieved.
AD7912/ AD7922*
SCLK DOUT DIN CS
AD7912/AD7922 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7912/AD7922. The CS input allows easy interfacing between the TMS320C541 and the AD7912/AD7922 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode (FSM = 1 in the serial port control register, SPC) with the internal serial clock CLKX (MCM = 1 in the SPC register) and the internal frame signal (TXM = 1 in the SPC register); therefore, both pins are configured as outputs. For the AD7922, the word length should be set to 16 bits (FO = 0 in the SPC register). This DSP allows frames with a word length of 16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are required, the FO bit should be set up to 16 bits, and 16 SCLKs are needed. For the AD7912, two trailing zeros are clocked out in the last two clock cycles. The values in the SPC register are as follows: FO = 0 FSM = 1 MCM = 1 TXM = 1 To implement the power-down mode on the AD7912/AD7922, the format bit, FO, can be set to 1, which sets the word length to 8 bits. The connection diagram is shown in Figure 39. Note that, for signal processing applications, the frame synchronization signal from the TMS320C541 must provide equidistant sampling.
AD7912/ AD7922*
SCLK
ADSP-218x*
SCLK DR DT RFS TFS
04351-0-037
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 40. Interfacing to the ADSP-218x
TMS320C541*
CLKX CLKR
DOUT DIN CS
DR DX
04351-0-036
FSX FSR
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 39. Interfacing to the TMS320C541
The timer registers are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, therefore, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, that is, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data might be transmitted or it might wait until the next clock edge.
Rev. 0 | Page 26 of 32
AD7912/AD7922
For example, the ADSP-2189 has a master clock frequency of 40 MHz. If the SCLKDIV register is loaded with the value of 3, then an SCLK of 5 MHz is obtained, and eight master clock periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the value 803 (803 + 1 = 804), then 100.5 SCLK occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling, because the transmit instruction occurs on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling is implemented by the DSP. low and a conversion starts. Likewise, by means of the Bits SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the frame sync signal) and SCK in the serial port are configured as outputs, and the MSB is shifted first. The values are as follows: MOD = 0 SYN = 1 WL2, WL1, WL0 depend on the word length FSL1 = 0, FSL0 = 0 FSP = 1, negative frame sync SCD2 = 1 SCKD = 1 SHFD = 0 Note that, for signal processing applications, the frame synchronization signal from the DSP563xx must provide equidistant sampling.
AD7912/ AD7922*
SCLK DOUT DIN CS
AD7912/AD7922 to DSP563xx Interface
The connection diagram in Figure 41 shows how the AD7912/ AD7922 can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The SSI is operated in synchronous and normal mode (SYN = 1 and MOD = 0 in the Control Register B, CRB) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in the CRB). Set the word length in the Control Register A (CRA) to 16 by setting bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7922. This DSP does not offer the option for a 14-bit word length, so the AD7912 word length is set up to 16 bits like the AD7922. For the AD7912, the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. To implement the power-down mode on the AD7912/AD7922, the word length can be changed to 8 bits by setting Bits WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the CRB register can be set to 1, which means that the frame goes
DSP563xx*
SCK SRD STD SC2
04351-0-038
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 41. Interfacing to the DSP563xx
Rev. 0 | Page 27 of 32
AD7912/AD7922 APPLICATION HINTS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7912/AD7922 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7912/ AD7922 are in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7912/AD7922. Avoid running digital lines under the device, because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7912/AD7922 to avoid noise coupling. The power supply lines to the AD7912/AD7922 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also very important. The analog supply should be decoupled with 10 F tantalum in parallel with 0.1 F capacitors to AGND. To achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the VDD and GND pins to a minimum with short track lengths connecting the respective pins.
Rev. 0 | Page 28 of 32
AD7912/AD7922 EVALUATING AD7912/AD7922 PERFORMANCE
The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2. The EVAL-CONTROL BRD2 can be used in conjunction with the AD7912CB/AD7922CB evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator to demonstrate and evaluate the ac and dc performance of the AD7912/AD7922. The software allows the user to perform ac (Fast Fourier Transform) and dc (histograms of codes) tests on the AD7912/AD7922. See the AD7912/AD7922 Technical Note for more information. The technical note is included in the software, and it can also be found on the www.analog.com website under the Design Tools link on the AD7912/AD7922 product page.
Rev. 0 | Page 29 of 32
AD7912/AD7922 OUTLINE DIMENSIONS
2.90 BSC
3.00 BSC
8 7 6 5
8
5
1.60 BSC
2.80 BSC
1 2 3 4
3.00 BSC
4
4.90 BSC
PIN 1 INDICATOR
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.90 0.87 0.84
0.65 BSC 1.95 BSC
0.15 0.00 0.38 0.22 COPLANARITY 0.10
1.00 MAX
0.20 0.08 8 4 0
0.23 0.08 SEATING PLANE
0.10 MAX
0.38 0.22
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-187AA
COMPLIANT TO JEDEC STANDARDS MO-193BA
Figure 42. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
Figure 43. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7912ARM AD7912ARM-REEL AD7912ARM-REEL7 AD7912AUJ-R2 AD7912AUJ-REEL7 AD7922ARM AD7922ARM-REEL AD7922ARM-REEL7 AD7922AUJ-R2 AD7922AUJ-REEL7 EVAL-AD7912CB2 EVAL-AD7922CB2 EVAL-CONTROL BRD23 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Linearity Error (LSB)1 0.5 max 0.5 max 0.5 max 0.5 max 0.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max Package Description 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead TSOT 8-lead TSOT 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead TSOT 8-lead TSOT Evaluation Board Evaluation Board Evaluation Control Board Package Option RM-8 RM-8 RM-8 UJ-8 UJ-8 RM-8 RM-8 RM-8 UJ-8 UJ-8 Branding C1A C1A C1A C1A C1A C1B C1B C1B C1B C1B Quantity 1 3000 1000 250 3000 1 3000 1000 250 3000
1 2 3
Linearity error here refers to integral nonlinearity. This evaluation board can be used standalone or in conjunction with the EVAL-CONTROL BRD2 for evaluation or demonstration purposes. This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, order a particular ADC evaluation board (EVAL-AD7922 CB, for example), the EVAL-CONTROL BRD2, and a 12 ac transformer. See the relevant evaluation board technical note for more information.
Rev. 0 | Page 30 of 32
AD7912/AD7922 NOTES
Rev. 0 | Page 31 of 32
AD7912/AD7922 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04351-0-4/04(0)
Rev. 0 | Page 32 of 32

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